1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit (IC) device and, more particularly, to a semiconductor IC device capable of generating clock signals.
2. Related Art
Generally, high-speed synchronous dynamic random access memory (SDRAM) devices employ write clock signals independently from read clock signals. In order to reduce current consumption, dedicated clocks are selectively activated in response to a read operation or a write operation.
FIG. 1 is a schematic block diagram of a conventional semiconductor IC device including a clock buffer. In FIG. 1, the clock generator 1 includes a write dock buffer 10 and a read dock buffer 20, wherein the write dock buffer 10 receives an external dock signal ‘CLK’ to generate a write dock signal ‘WT_CLK’. The read dock buffer 20 receives the external clock signal ‘CLK’ to generate a read dock signal ‘RD_CLK’. Accordingly, the write dock signal ‘WT_CLK’ and the read clock signal ‘RD_CLK’ can be activated in response to the external clock signal ‘CLK’. However, reset operational modes of the write clock signal ‘WT_CLK’ and the read clock signal ‘RD_CLK’ are controlled in different manners.
As shown in FIG. 1, the write clock signal ‘WT_CLK’ is reset in response to only a refresh signal ‘REF’ for the purpose of a specific test. The read clock signal ‘RD_CLK’ is reset in response to an idle operational mode signal ‘IDLE’, as well as the refresh signal ‘REF’. Thus, the idle mode includes a precharge mode and a power down mode, wherein, in the idle mode, the semiconductor IC device is not operated. For example, if the idle mode includes a test mode to drive a write circuit part (not shown), then the write clock signal must be driven even in the idle mode. Accordingly, the write clock signal ‘WT_CLK’ is continuously provided even in the idle mode, so that the standby current of the semiconductor IC device is increased.